Your AI agent designs the PCB.
You watch and steer.
Fragua is a desktop tool that exposes a small, deterministic API for AI agents. The agent drives the schematic, the placement, the auto-router, the rule checks, and ships a fab-ready zip in a single loop. The human watches, redirects when needed, and clicks "order".
What it does
One small surface for the agent
A line-oriented script DSL on a stateless local HTTP API. The agent
sends multi-line scripts; each verb is one tool call. The full
reference is printed at startup and at GET / — no SDK,
no protocol negotiation, no hidden state.
Real router, not a wrapper
Multi-layer Theta* / A* with rip-up-and-reroute, optional negotiated
congestion, fine-pitch escape-slot fanout, and an organic post-pass.
Experimental topological engine available. Per-net and rule-area
widths / clearances from NetClass. No FreeRouting, no
kicad-cli.
Real placer too
Two-stage placer: electrostatic global placement, then simulated annealing legalisation (HPWL + body gap + congestion + crossings). Edge planning for connectors, elevated modules on headers. The agent names which refs may move; everything else stays where the human put it.
Validation at every step
ERC catches netlist bugs (multiple drivers, unpowered power rails, missing decoupling caps). DRC catches geometry bugs (clearance, annular ring, narrow trace). Manufacturing-DRC catches what your chosen fab will refuse before you upload.
Fab-ready zip in one verb
pack fab=jlcpcb runs the whole validation pipeline,
emits Gerbers + Excellon drills + provider-specific BOM and CPL,
bundles them with a README, and drops a single
<project>-jlcpcb.zip ready to upload. JLCPCB,
PCBWay and a generic format are built in; new houses are one match
arm away.
Human stays in the loop
The desktop app shows the live state — every footprint placement, every routed trace, every DRC violation. Click a component, drag it, watch the agent re-plan. Nobody is locked out by either side.
End-to-end, in 25 lines
What the agent might send to POST /script. Every line is
one verb; each verb commits to the project state and emits an event the
UI repaints from. The full pipeline — ERC, placement, routing, fab pack —
happens server-side in milliseconds-to-seconds.
# Board, with rounded corners. outline 80 30 radius=2 # Net classes for the rails — GND on both layers as a pour. class ground pour=both class power width=0.4 # Schematic (subset). sym U1 ic key=esp32_s3_zero pin 1 L 3V3 role=power_in pin 2 L GND role=power_in pin 12 L SCL role=bidir pin 11 L SDA role=bidir sym C1 capacitor key=c_0603 value=100nF lcsc=C14663 sym R1 resistor key=r_0603 value=4.7k lcsc=C25814 sym R2 resistor key=r_0603 value=4.7k lcsc=C25814 net GND U1.GND C1.2 class=ground net +3V3 U1.3V3 C1.1 R1.1 R2.1 class=power net SDA U1.SDA R1.2 net SCL U1.SCL R2.2 # Pre-flight schematic check. erc # Footprints + initial placement, then SA on the loose parts. palette U1 esp32_s3_zero palette C1 c_0603 palette R1 r_0603 palette R2 r_0603 place U1 20 15 auto-place C1 R1 R2 seed=42 # Route, then ship the zip. route pack fab=jlcpcb out=~/Downloads
Install & run
Fragua is a single Go binary: local HTTP API and a browser UI. Pre-built binaries are on GitHub Releases; or build from source:
# One-liner install (macOS arm64/x64, Linux x64). curl -fsSL https://raw.githubusercontent.com/mentasystems/fragua/master/scripts/install.sh | sh # From source: git clone https://github.com/mentasystems/fragua.git cd fragua go build -o fragua ./cmd/fragua # Launch (the `run` subcommand starts the API + UI). ./fragua run # …or open an existing project file (autosave bound to it). ./fragua run /path/to/board.fragua # Bare `fragua` prints usage + the full script reference and exits. ./fragua
The browser opens, and a stateless local HTTP API starts on
127.0.0.1:7878 (override with FRAGUA_API_ADDR).
Point any agent that can make HTTP calls at it:
# Discover the full action surface (also GET /help). curl -s http://127.0.0.1:7878/ # Liveness + headless board PNG. curl -s http://127.0.0.1:7878/health curl -s 'http://127.0.0.1:7878/screenshot?view=board&width=1600' -o board.png # Run a script. curl -s http://127.0.0.1:7878/script \ -H 'content-type: application/json' \ -d '{"script":"outline 80 30 radius=2\nstatus"}'
Replies are text/plain: per-line outcomes, plus an unsaved-session warning if the project isn't bound to a file yet.
Status
v1.1.x. Every bullet below works in the current master; the "what's next" list is what the maintainers are most likely to work on, not a commitment.
Today
- Schematic with symbols, pins (electrical roles), nets, net classes, multi-sheet ports.
- Library of footprints with photos, datasheets, LCSC IDs, MPNs, edge-mount and elevated bodies.
- Two-stage auto-placer (ePlace global + SA legalisation, edge-plan, decoupling ring, compact).
- Auto-router (RR&R + optional negotiation + fine-pitch escape fanout + organic pass; experimental topo engine).
- ERC (incl. decoupling / I²C heuristics), DRC, manufacturing-DRC; rule areas and fab-rules.
- Auto-pour from net classes; multi-layer stackup; polygonal outlines, milled cutouts, NPTH holes.
- One-shot
pack(JLCPCB / PCBWay / generic zip) + ODB++.tgzfrom the UI. - Headless
GET /screenshotandscreenshotscript verb for agent verification. - Live SVG canvas with pan/zoom and click-to-inspect.
What's next
- An embedded LCSC catalogue subset so the agent doesn't have to look up part numbers by hand.
- Richer heuristic ERC: "USB without ESD", "MCU without crystal load caps".
- ODB++ export as a first-class script verb (UI export already works).
- Real-time cost estimation against the chosen fab's pricing tier.
- More fab providers (OSHPark, Aisler, Eurocircuits).
- Frontend: click a net to highlight it, jump-to from the DRC violation list.
Open source
MIT licensed. See CONTRIBUTING.md for what's in scope. Issues and PRs welcome — especially adding fab providers, library parts, and bug fixes from real-world designs.
Built in Go. No kicad-cli, no
FreeRouting wrapper, no shell-out. Every file format read or written
is implemented in this repo.