Your AI agent designs the PCB.
You watch and steer.

Fragua is a desktop tool that exposes a small, deterministic API for AI agents. The agent drives the schematic, the placement, the auto-router, the rule checks, and ships a fab-ready zip in a single loop. The human watches, redirects when needed, and clicks "order".

Get the source Run it locally

What it does

One small surface for the agent

A line-oriented script DSL on a stateless local HTTP API. The agent sends multi-line scripts; each verb is one tool call. The full reference is printed at startup and at GET / — no SDK, no protocol negotiation, no hidden state.

Real router, not a wrapper

Two-layer A* with rip-up-and-reroute, negotiated congestion bias, and Steiner-style multi-source construction. Per-net trace widths and clearances honoured from NetClass declarations. No FreeRouting, no kicad-cli.

Real placer too

Simulated annealing on HPWL plus a soft body-to-body gap penalty plus a rasterised pad-bbox congestion proxy. The agent passes the list of refs that may move; everything else stays where the human put it.

Validation at every step

ERC catches netlist bugs (multiple drivers, unpowered power rails, missing decoupling caps). DRC catches geometry bugs (clearance, annular ring, narrow trace). Manufacturing-DRC catches what your chosen fab will refuse before you upload.

Fab-ready zip in one verb

pack fab=jlcpcb runs the whole validation pipeline, emits Gerbers + Excellon drills + provider-specific BOM and CPL, bundles them with a README, and drops a single <project>-jlcpcb.zip ready to upload. JLCPCB, PCBWay and a generic format are built in; new houses are one match arm away.

Human stays in the loop

The desktop app shows the live state — every footprint placement, every routed trace, every DRC violation. Click a component, drag it, watch the agent re-plan. Nobody is locked out by either side.

End-to-end, in 25 lines

What the agent might send to POST /script. Every line is one verb; each verb commits to the project state and emits an event the UI repaints from. The full pipeline — ERC, placement, routing, fab pack — happens server-side in milliseconds-to-seconds.

# Board, with rounded corners.
outline 80 30 radius=2

# Net classes for the rails — GND on both layers as a pour.
class ground pour=both
class power  width=0.4

# Schematic (subset).
sym U1 ic key=esp32_s3_zero
  pin 1 L 3V3 role=power_in
  pin 2 L GND role=power_in
  pin 12 L SCL role=bidir
  pin 11 L SDA role=bidir
sym C1 capacitor key=c_0603 value=100nF lcsc=C14663
sym R1 resistor  key=r_0603 value=4.7k  lcsc=C25814
sym R2 resistor  key=r_0603 value=4.7k  lcsc=C25814

net GND  U1.GND C1.2 class=ground
net +3V3 U1.3V3 C1.1 R1.1 R2.1 class=power
net SDA  U1.SDA R1.2
net SCL  U1.SCL R2.2

# Pre-flight schematic check.
erc

# Footprints + initial placement, then SA on the loose parts.
palette U1 esp32_s3_zero
palette C1 c_0603
palette R1 r_0603
palette R2 r_0603
place U1 20 15
auto-place C1 R1 R2 seed=42

# Route, then ship the zip.
route
pack fab=jlcpcb out=~/Downloads

Install & run

Fragua is a Rust workspace + a TypeScript frontend hosted in a Tauri 2 shell. Build it from source for now — pre-built binaries will follow.

git clone https://github.com/mentasystems/fragua.git
cd fragua

# Build the embedded frontend bundle once.
npm --prefix frontend install
npm --prefix frontend run build

# Run the desktop app.
cargo run --release --bin fragua

# …or open an existing project file.
cargo run --release --bin fragua /path/to/board.fragua

The window opens, and a stateless local HTTP API starts on 127.0.0.1:7878. Point any agent that can make HTTP calls at it:

# Discover the full action surface.
curl -s http://127.0.0.1:7878/

# Run a script.
curl -s http://127.0.0.1:7878/script \
  -H 'content-type: application/json' \
  -d '{"script":"outline 80 30 radius=2\nstatus"}'

Replies are text/plain: per-line outcomes, plus an unsaved-session warning if the project isn't bound to a file yet.

Status

Pre-1.0. Every bullet below works in the current master; the "what's next" list is what the maintainers are most likely to work on, not a commitment.

Today

Schematic with symbols, pins (with electrical roles), nets, and net classes.
Library of footprints with photos, datasheets, LCSC IDs and MPNs.
Auto-placer (SA on HPWL + gap penalty + congestion proxy).
Auto-router (RR&R + negotiated congestion + Steiner-style multi-source A*).
ERC, DRC, manufacturing-DRC; per-fab rules for JLCPCB / PCBWay / generic.
Auto-pour from net classes (GND-on-both-layers in one declaration).
Rounded board outlines (renderer + router inset + Gerber arcs).
One-shot pack verb producing a ready-to-upload zip.
Live SVG canvas with pan/zoom and click-to-inspect.

What's next

An embedded LCSC catalogue subset so the agent doesn't have to look up part numbers by hand.
Heuristic ERC: "USB without ESD", "MCU without crystal load caps".
3D / mechanical preview (component heights → STEP export).
Real-time cost estimation against the chosen fab's pricing tier.
More fab providers (OSHPark, Aisler, Eurocircuits).
Frontend interactivity: click a net to highlight it, jump-to from the DRC violation list.

Open source

MIT licensed. See CONTRIBUTING.md for what's in scope. Issues and PRs welcome — especially adding fab providers, library parts, and bug fixes from real-world designs.

Built in Rust + Tauri 2 + TypeScript. No kicad-cli, no FreeRouting wrapper, no shell-out. Every file format read or written is implemented in the workspace.

Your AI agent designs the PCB.You watch and steer.